Summary: Introduce the contact-type IC card and read and write the principle in detail; Combine one and read and write the chip, system that can operate 6 slices of contact-type IC cards at the same time on the basis of being different, run side by side communication, half duplexing serial communication and the intersection of I2C and several different the intersection of interface and IC card of form of communication read and write whom chip go on in detail, compare and analyse including.

Keyword: ISO/IEC7816 the intersection of interface and the intersection of technology and contact-type IC card walk abreast communication half duplexing serial communication I2C bus communication

Foreword

IC card Integrated Circuit Card, integrated circuit card Ones that present following magnetic stripe card and a new kind of information tools. The IC card calls the intelligent card smart card in some countries and regions too , smart card intelligent card , little circuit card microcircuit card Or the microchip card,etc.. It accords with ISO 7816 standard card base that it imbeds a microelectronic chip, make into the card form; Have already very applied to including a lot of fields such as the finance, traffic, social insurance widely.

IC card person who read and write IC card and bridge among the application system, call that the intersection of interface and Interface Device, IFD of apparatus, in the intersection of ISO and international standard . CPU in IFD links with IC card and carries on communication through a interface circuit. The interface circuit of the IC card is the essential part in the reading and writing device of the IC card, based on different real application systems, can choose, run side by side communication, half duplexing serial communication and the intersection of I2C and the intersection of communication,etc. and different IC cards read and write the chip.

Technological principle of a contact-type IC card of interface

If the IC card reading and writing device can read and write the IC card which accords with ISO7816 standard. The interface circuit of the IC card carries on the only passway of communication as CPU in IC card and IFD, in order to guarantee the communication and security and reliable of data interchange, its electric signal produced must meet the following particular requirement.

1.1 Finish the recognition operation that the IC card is inserted and withdrawn from

Recognition inserting and withdrawing from the IC card with interface circuit of the IC card, namely activation and release of the card, very strict time sequence is required. If can’t meet the corresponding requirement, the IC card can’t be operated normally; Will damage the IC card or IC card reading and writing device when being serious.

1Activate the course

For start operation in card, interface circuit should order activate circuit according to the show of Fig. 1:

RST is in L state;

According to the type of the card chosen, add electric As or Bs to VCC, the electric characteristic of VCC is shown in Table 1 under the normal running condition;

Electric characteristic of the normal running terms VCC of Table 1

Symbol minimum Condition Vvcc/V of the maximum 4.52.7 　　　 5.53.3 A B Icc/mA 60500.5 A in most large to allow the intersection of frequency and B, in most loud to allow the intersection of frequency and clock stop

VPP becomes the idle state;

I/O of the circuit of interface should locate in and receive the state;

Provide the clock signal A card 1- 5MHz, B card 1- 4MHz for CLK of the IC card .

,Add the clock signal to CLK of the IC card in t’ a time. I/O circuit should be added in the clock signal in 200 clock cycles ta of CLK Located and hinder the state Z ta time is after t’ a high inside . The clock is added after CLK, keep RST as state L at least 400 cycles tb Make the card reset tb is after t’ a . In time t’ b, RST is located the state H. Rise should promising in I/O signal at RST along after 400~40 000 clock cycletc Begin tc is after t’ b inside .

In a situation that RST is in the state H, if the answer signal does not begin yet within 40 000 clock cycles, the signal on RST will be returned to the state L, and the IC card interface circuit releases the IC card according to the show of Fig. 2.

2Release the course

When information exchange finishes or fails for example, it is responded to that there is no card or the card is shifted out ,The circuit of interface answers according to the show of Fig. 2 time sequence releases the circuit:

RST should be put as the state L;

CLK should be put for the state L unless the clock has already been stopped on the state L ;

VPP should be releasedif it has already been activated ;

I/O should be put for the state A not there is not a concrete definition within td time ;

VCC should be released.

1.2 Provide the steady power for card through the contact

The IC card interface circuit should be able to provide the corresponding and steady electric current for IC card within the range of fixed voltage of Table 1.

1.3 Provide the steady clock for card through the contact

The IC card interface circuit provides the clock signal for card. The actual frequency range of the clock signal should be in the following ranges during resetting and replying: A card, the clock should be in 1- 5MHz; B card, the clock should be in 1- 4MHz.

After resetting, reset replies ATR received F clock frequency varies the factor in the signal With D one bit of rate adjusts the factor Come to fix.

The work period of the clock signal should be 40%- 60% of steady operation period. When the frequency is transformed from a value into another value, should pay attention to guaranteeing not to have it than 40% of the shorter pulses of short cycle.

2 odd kinds of contrasts and analysis of realizing the way

The IC card in IFD reads and writes the chip, in order to visit directly, another 29 registers will pass the register of addresses of index IAR Come to visit. It visits and is divided into two steps: The first step of addresses that is the register that will visit indirectly is written in IAR register; Second step is from the register of the data DR China reads the data or writes into the data in DR register, to finish the visit to register visiting indirectly.

The following C51 subprogram is the subprogram in the register to be visited indirectly of writing the one byte gets based on Fig. 3.

#define SN2_IAR XBYTE[0x0000]

#define SN2_DR XBYTE[0x0100]

void WriteByteIndexedBYTE bIndex, BYTE bData {

P1.0 =0;

SN2_IAR = bIndex;

SN2_DR = bData;

}

2.2.2 Software design of WatchCore

WatchCore does not take UART of the hardware, its serial communication is to use the software to be real-time and artificial. The communication speed adopts 9600bps; The communication byte form is an initial location, location of 8 data, location of an even check-up, 2 stop the location. TXD and RXD electric signal is the standard CMOS level, can link with circuit of TTL directly. The following is a data packet form at the time of the communication.

1Order to wrap up

It is CPU data to WatchCore in a reading and writing device of a IC card to order to wrap up, it bag of forms are as follows:

NAD PCB LEN DATA BCC

NAD chooses for the chuck, NAD=0×00/0x12it is a main chuck, NAD =0×13 is from the chuck;

PCB has no relations with communicating, CPU card T =Use at 1 o’clock, PCB usually sets up as 0×00;

LEN, for the byte length only the byte of section DATA is counted of the data ;

DATA, in order to send the order the standard of ordering to consult ISO7816-4 of WactchCore or IC Carney ;

It is in BCC different or check-up that all byte is different at byte 4 segment section BCC ago or and .

2Data packet

The data packet is the data that WatchCore returns after receiving the order bag, its bag of forms are as follows:

* NAD order the intersection of NAD and the intersection of high or low prices and 4 return after exchanging of byte in the bag WatchCore. For example, order to wrap up and send NAD =0×12, WatchCore recycle NAD * back to =0×21;

Other all Section are the same with ordering the bag.

Communication gives an example the following data are indicated by sexadecimal number system

Reset the main card

Send the order to wrap up as follows:

12 00 05 00 12 00 00 00 05

If there is no card in the main chuck, then WatchCore returns:

21 00 02 62 00 41

If the main chuck has a T =0 CPU cards, may return:

21 00 11 3B 7A 18 00 00 21 08 11 12 13 14 15 16 17 18 90 00 D8

2.2.3 Software design of TDA8020

The communication of CPU is carried on by means of I2C bus in TDA8020 and IFD. Through I2C interface, CPU in IFD can send the order or read the state of TDA8020 to TDA8020. TDA8020 has two addresses that choose the pin SAD0 and SAD1 . In Fig. 3, these two addresses choose earthing the pin, it is 40H and 48H to correspond to I2C bus address of two IC cards respectively. If there are other I2C bus devices in the system, can seek the location according to the way of Table 2.

I2C address of the table 2 TDA8020 chooses the table

SAD1 SAD0 CARD1 CARD 2 0 0 40H 48H 0 1 42H 4AH 1 0 46H 4CH 1 1 48H 4EH

1Write to TDA8020 into the form of the order

Fig. 4 is written to TDA8020 into the form of the order. According to the show of Fig. 3, it is 40H to the address of the card 1 and byte written.

Among them control the meaning of everybody of byte to be set out in Table 3.

Order to control the meaning of everybody of byte in Table 3

The location of name proves START and/ STOP 0 are 1, a cold activation time sequence that resets emerges: 0,produce by every one, because preface 1 of WARMs is for 1 while releasing, can’t produce because preface 3/5V 2 is for 1 while resetting one of heats, can’t presume whether there are for 3V in voltage on operation of card; It is 0, presume the operation voltage of the card is that 5V PDOWN 3 is 1, presume the card in order to make the electric mode; It is 0, presume the card is 1 as normal working mode CLKPD 4, presume the electric mode lower CLK to stop in the high level; It is 0, presuming the electric mode lower CLK stops the clock frequency of job when low level CLKSEL15 two presume that is blocked in the normal work pattern and sees the list 4 CLKSEL26 I/OEN 7 I/ O can enable the location. It is 1 o’clock, I/O links with I/Ouc; It is 0 o’clock, I/Ouc high hinders the state

2Read the data form of the state within TDA8020

Read the form of the state from TDA8020. According to the show of Fig. 3, it is 41H to the address of the card 1 and byte read.

Among them everybody’s meaning is set out in Table 5 in the byte of state.

The clock frequency of the job of Table 4 is chosen the way

CLKSEL2 CLKSEL1 CLOCK OU 00 CLKIN/800 CLKIN/410 CLKIN/211 CLKIN

Meaning of everybody of byte of state of Table 5

The location of name explains the state instruction of PRES0 card. It is 1 o’clock, measure the card: It is 0 o’clock, without the card PRESL 1 is 1 to measure toing, the state of the card has not been read yet; When it is 0 o’clock, it is high to already read I/O 2 I/O out in state of the card, this is 1; When I/O is low, this is that 0 SUPL 3 is 1 o’clock, show the watch-dog of the power has already been exported, it is 1 after having the electricity, until it is 1 as 0 PROT 4 after reading, show overheated or the intersection of overload and the intersection of state and MUTE 5 show, block, send out the intersection of ATR and the intersection of signal and EARLY 6 show, block on in front of fixed time 1 o’clock within fixed time 1 o’clock It is 1 o’clock to already send out ATR signal ACTIVE 7, the card is in activating state; It is 0 o’clock, the card is in releasing the state

3 is summarized

The above has recommended the IC card of three kinds of different interface to read and write the chip in detail. These three differences with greatest way lie in it and communication way of CPU in IFD is different, and all accord with the standard of ISO/IEC7816. However, these three have some places that some differences exist to read and write the chip.

TDA8020 supports A type and B card, but WatchCore and SNIPER II CST56I01 only support the A card. Though one is a card choice in the register within SNIPER II CST56I01, only support the A card.

TDA8020 and SNIPER II CST56I01 its ESD protect Damien 6kV, but WatchCore has no ESD to protect the function.

TDA8020 can support the power of the card directly, and flow and protect the function; But WatchCore and SNIPER II CST56I01 only realizes by putting the tube in a work, and not flowed and protected the function, only connect and protect the circuit can reset the fuse such as adding .

As to the way of its interface, the connection of CPU in TDA8020 and WatchCore though and IC card reading and writing device of one bunch of mouths of I2C bus is convenient, but general CPU does not have surplus bus interface of bunches of mouths and I2C that is given to these two chips, generally imitate the bus interface of one bunch of mouths and I2C and could carry on communication with mouth of common I/O. And SNIPER II CST56I01 and CPU in the IFD walk abreast communication though connecting wire more, corresponding software its much more convenient.

In sum, these three IC cards read and write the chip and have nothing in common with each other, while realized and is employed, only select different reading and writing the chip for use according to different resource situations.

Article source: Intelligent clever network